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lt4256-3 1 42563fa the lt 4256-3 is a high voltage hot swap tm controller that allows a board to be safely inserted and removed from alive backplane. an internal driver controls the high side n-channel mosfet gate for supply voltages ranging from 10.8v to 80v. the part features an open-circuit detect (open) output that indicates abnormally low load current conditions. the lt4256-3 also features an adjustable analog foldback current limit. if the supply remains in current limit for more than a programmable time, the n-channel mosfet shuts off, the pwrgd output asserts low and the lt4256-3 either automatically restarts after a time-out delay or latches off until the uv pin is cycled low (depending on the status of the retry pin). the pwrgd output indicates when the output voltage rises above a programmed level. an external resistor string from v cc provides programmable undervoltage and overvoltage protection.the lt4256-3 is available in a 16-lead ssop package. hot board insertion electronic circuit breaker/power bussing industrial high side switch/circuit breaker 24v/48v industrial/alarm systems ideally suited for 12v, 24v and 48v distributedpower systems 48v telecom systems , ltc and lt are registered trademarks of linear technology corporation. allows safe board insertion and removal from alive backplane controls supply voltage from 10.8v to 80v foldback current limiting open circuit and overcurrent fault detect drives an external n-channel mosfet automatic retry or latched off operationafter overcurrent fault programmable supply voltage power-up rate open mosfet detection 1% over and undervoltage detection accuracy available in a 16-lead ssop package positive high voltage hot swap controller with open-circuit detect 4256 ta01 0.020 ? lt4256-3 sense v cc gate fb v out pwrgd retry uvov timer gnd v in 48v gnd (short pin) irf540 cmpz5241bs11v 4.02k 4.02k 64.9k 100 ? 4.02k 10 ? 36.5k pwrgd v out 48v2a 51k c l 33nf 0.01 f 10nf open smat70a uv = 36vov = 73v pwrgd = 40v + 48v, 2a hot swap controller features descriptio u applicatio s u typical applicatio u lt4256-3 start-up behavior hot swap is a trademark of linear technology corporation.all other trademarks are the property of their respective owners. v in 50v/div v out 50v/div pwrgd 50v/div 2.5ms/div c l = 225 f 42563 ta02 inrush current 500ma/div contact bounce downloaded from: http:///
lt4256-3 2 42563fa (note 1) supply voltage (v cc ) ................................ 0.3 to 100v sense, pwrgd ....................................... 0.3 to 100v gate voltage (note 2) .................... 0.3v to v cc + 10v gate maximum current ..................................... 200 a v out .......................................................... 3v to 100v fb, uv, open ............................................. 0.3 to 44v ov .............................................................. 0.3 to 18v retry ........................................................ 0.3 to 15v timer voltage ......................................... 0.3v to 4.3v maximum input current (timer) ....................... 100 a operating temperature lt4256-3c ............................................. 0 c to 70 c lt4256-3i ......................................... 40 c to 85 c storage temperature range ................ 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c absolute axi u rati gs w ww u consult ltc marketing for parts specified with wider operating temperature ranges.note: nc is a pin that is ?ot connected. package/order i for atio uu w order part number gn part marking 4256342563i lt4256-3cgnlt4256-3ign electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 48v unless otherwise noted. symbol parameter conditions min typ max units v cc operating voltage 10.8 80 v i cc operating current 1.8 3.9 ma v uvlh undervoltage threshold v cc low-to-high transition 3.96 4 4.04 v v uvhys hysteresis 0.25 0.4 0.55 v i inuv uv input current uv 1.2v 0.1 1 a uv = 0v ?.5 3 a v uvrth fault latch reset threshold voltage 0.4 0.85 1.2 v v ovlh overvoltage threshold v cc low-to-high transition 3.96 4 4.04 v v ovhys hysteresis 0.25 0.4 0.55 v i inov ov input current 0v ov < 7v 0.1 1 a v open open-circuit voltage threshold (v cc ?v sense ) 1.5 3 6.5 mv v olopen open output low voltage i o = 2ma 0.20 0.5 v i o = 5ma 0.75 1.3 v i inopen leakage current v open = 5v 0.1 1 a v sensetrip sense pin trip voltage (v cc ?v sense ) fb = 0v 71 42 2 m v fb 2v 45 55 65 mv i insns sense pin input current v sense = v cc 40 70 a i pu gate pull-up current charge pump on, ? v gate = 7v ?6 32 63 a i pd gate pull-down current any fault, v gate > v out 40 62 80 ma i pdl v out pull-down current, fault condition any fault, v gate = v out + ? v gatel , 130 a v out = 48v ? v gate external n-channel gate drive (note 2) v gate ?v out , 10.8v v cc 20v 4.5 8.8 12.5 v 20v v cc 80v 10 11.6 12.8 v ? v gatel external n-channel gate drive, fault condition v gate ?v out , v out = 48v 2 v 12 3 4 5 6 7 8 top view gn package 16-lead plastic ssop 1615 14 13 12 11 10 9 uvov nc open pwrgd nc retry gnd v cc sensenc gate v out ncfb timer t jmax = 125 c, ja = 130 c/w order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbflead free part marking: http://www.linear.com/leadfree/ downloaded from: http:///
lt4256-3 3 42563fa v fb fb voltage threshold fb high-to-low transition 3.95 3.99 4.03 v fb low-to-high transition 4.20 4.45 4.65 v v fbhys fb hysteresis voltage 0.3 0.45 0.60 v v olpgd pwrgd output low voltage i o = 1.6ma 0.25 0.4 v i o = 5ma 0.60 1.0 v i pwrgd pwrgd pin leakage current v pwrgd = 80v 0.1 1 a i infb fb input current fb = 4.5v 0.1 ? a i timerpu timer pull-up current timer = 3v, during fault 63 105 147 a i timerpd timer pull-down current timer = 3v 1.5 3 5 a v thtimer timer shutdown threshold c timer = 10nf 4.3 4.65 5 v d timer duty cycle (retry mode) 1.5 3 4.5 % v retryth retry threshold 0.4 0.85 1.2 v i inrtr retry input current retry = gnd 87 ?30 a t phluv uv low to gate low c gate = 100pf 1.7 3 s t plhuv uv high to gate high c gate = 100pf 6 9 s t phlfb fb low to pwrgd low 0.8 2 s t plhfb fb high to pwrgd high 3.2 5 s t phlsense (v cc ?v sense ) high to gate low v cc ?v sense = 275mv 1 3 s electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 48v unless otherwise noted. symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: an internal clamp limits the gate pin to a minimum of 10v above v cc . driving this pin to a voltage beyond the clamp voltage may damage the part. typical perfor a ce characteristics uw i cc vs temperature sense regulation voltage vs temperature i cc vs v cc temperature ( c) ?0 10 sense regulation voltage (mv) 15 20 48 58 ?5 02 55 0 42563 g01 75 100 53 fb = 0v fb > 2v v cc (v) 10 2.0 2.5 3.5 40 60 42563 g02 1.51.0 20 30 50 70 80 0.5 0 3.0 i cc (ma) temperature ( c) ?0 0 i cc (ma) 0.5 1.0 1.5 2.5 ?5 02 55 0 42563 g03 75 100 2.0 v cc = 48v specifications are at t a = 25 c unless otherwise noted. downloaded from: http:///
lt4256-3 4 42563fa typical perfor a ce characteristics uw gate pull-up currentvs temperature gate pull-down currentvs temperature timer currents vs v cc timer currents vs temperature temperature ( c) ?0 ?0 gate pull-up current ( a) ?5 ?0 ?0 0 ?5 02 55 0 42563 g04 75 100 ?0 ?5 ? ?5 32 a @ 25 c temperature ( c) ?0 56 gate pull-down current (ma) 57 58 60 63 ?5 02 55 0 42563 g05 75 100 62 59 61 v gate ?v out voltage vs temperature temperature ( c) ?0 10.0 v gate ?v out voltage (v) 10.5 11.0 12.0 14.0 ?5 02 55 0 42563 g07 75 100 13.0 13.5 11.5 12.5 v cc = 80v v cc = 48v v cc = 20v v cc (v) 10 i timer ( a) 0 2.5 5.0 40 60 42563 g09 ?0 ?00 20 30 50 70 80 ?20 ?40 pull-up current pull-down current timer shutdown thresholdvs temperature temperature ( c) ?0 0 timer shutdown threshold (v) 4.2 4.4 4.8 5.4 ?5 02 55 0 42563 g10 75 100 5.2 4.6 5.0 specifications are at t a = 25 c unless otherwise noted. gate pull-down capability vs v cc below minimum operating voltage v cc (v) 0 0 i gate (ma ) 10 20 30 40 60 2 468 42563 g17 10 12 50 v gate ?v out voltage vs temperature temperature ( c) ?0 0 v gate ?v out voltage (v) 2 4 8 14 ?5 02 55 0 42563 g06 75 100 12 6 10 v cc = 10.8v v cc = 12v v cc = 18v uv current vs uv voltage v uv (v) 01234 ?.4 i uv ( a) ?.2 0.8 0.6 0.4 40 0.4 42563 g18 ?.0 10 20 30 50 0.2 0 0.2 temperature ( c) ?0 ?40 ?20 i timer ( a) ?00 ?0 0 5.0 ?5 02 55 0 42563 g08 75 100 2.5 pull-up current pull-down current downloaded from: http:///
lt4256-3 5 42563fa fb thresholds vs temperature open output voltage vs i open fb current vs fb voltage open threshold voltagevs temperature pwrgd output voltagevs i pwrgd ov current vs ov voltage i open (ma) 0 0 v open (v) 2 4 6 2 4 68 42563 g13 10 8 10 1 3 5 7 9 12 temperature ( c) ?0 0 0.5 open threshold voltage (mv) 1.5 2.5 3.5 5.0 ?5 02 55 0 42563 g14 75 100 4.5 1.0 2.0 3.0 4.0 v cc ?v sense i pwrgd (ma) 0 0 v pwrgd (v) 1 2 3 4 6 2 468 42563 g15 10 12 5 temperature ( c) ?0 3.9 4.0 fb thresholds (v) 4.1 4.2 4.3 4.5 ?5 02 55 0 42563 g16 75 100 4.4 h-l threshold l-h threshold v ov (v) 0 ?0 i ov ( a) 0 50 100 150 200 250 51 01 52 0 42563 g19 v fb (v) 0 0.4 i fb ( a) 0.3 0.2 0.1 0 0.1 0.2 10 20 30 40 42563 g20 50 typical perfor a ce characteristics uw specifications are at t a = 25 c unless otherwise noted. uv thresholds vs temperature temperature ( c) ?0 3.5 3.6 uv thresholds (v) 3.7 3.8 3.9 4.1 ?5 02 55 0 42563 g11 75 100 4.0 h-l threshold l-h threshold ov thresholds vs temperature temperature ( c) ?0 3.5 3.6 ov thresholds (v) 3.7 3.8 3.9 4.1 ?5 02 55 0 42563 g12 75 100 4.0 h-l threshold l-h threshold downloaded from: http:///
lt4256-3 6 42563fa pi fu ctio s uuu uv (pin 1): undervoltage sense input. uv is an input that enables the output voltage. when uv is driven above 4v,gate will start charging and the output turns on. when uv goes below 3.6v, gate discharges and the output shuts off. pulsing uv to below 0.4v for at least 5 s after a current limit fault cycle resets the fault latch (when retry pin islow, commanding latch off operation) and allows the part to turn back on. this command is only accepted after timer is discharged below 0.65v. to disable uv sensing, connect the pin to a voltage between 5v and 44v. ov (pin 2): overvoltage sense input. ov is an input that disables the output voltage. if ov ever goes above 4v,gate is discharged and the output shuts off. when ov goes below 3.6v, gate starts charging and the output turns back on. to disable overvoltage sensing, connect pin to ground. nc (pins 3, 6, 11, 14): no connect. not connected to any internal circuitry.open (pin 4): open circuit detect output. this pin is an open collector output that releases and is pulled highthrough an external resistor if the load current is less than (3mv)/r5. pwrgd (pin 5): power good output. pwrgd is pulled low whenever the voltage on fb falls below the high-to-lowthreshold voltage. it goes into a high impedance state when the voltage on fb exceeds the low-to-high threshold voltage. an external pull-up resistor can pull pwrgd to a voltage higher or lower than v cc . retry (pin 7): current fault retry input. retry com- mands the operational mode of the current limit. if retryis floating, the lt4256-3 automatically restarts after a current fault. if it is connected to a voltage below 0.4v, it will latch off after a current fault (which requires that uv be cycled low in order to start normal operation again). gnd (pin 8): device ground. this pin must be tied to a ground plane for best performance.timer (pin 9): timing input. an external timing capacitor from timer to gnd programs the maximum time the partis allowed to remain in current limit. when the part goes into current limit, a 105 a pull-up current source starts to charge the timing capacitor. when the voltage on timerreaches 4.65v (typ), gate is pulled low; the timer pull- up current will be turned off and the capacitor is discharged by a 3 a pull-down current. when timer falls below 0.65v (typ), gate turns on again if retry is high (if retry islow, uv must be pulsed low to reset the internal fault latch before gate will turn on). if retry is grounded and uv is not cycled low, gate remains latched off and timer will be discharged to near ground. uv must be cycled low after timer has discharged below 0.65v (typ) to reset the part. if retry is floating or connected to a voltage above its 1.2v threshold, the lt4256-3 automatically restarts after a current fault. under an output short-circuit condition, the lt4256-3 cycles on and off with a 3% on-time duty cycle. fb (pin 10): power good comparator input. fb monitors the output voltage through an external resistive divider.when the voltage on fb is lower than the high-to-low threshold of 3.99v, pwrgd is pulled low and released when fb is pulled above the 4.45v low-to-high threshold. the voltage present on fb affects foldback current limit (see figure 8 and related discussion). v out (pin 12): output voltage sense input. this pin should be connected to the source of the external mosfet.it is used to sense when the mosfet is shut off (during any fault mode) and to reduce the pull-down current on gate. this protects the lt4256-3 from excessive power dissipa- tion when large output capacitors are used. downloaded from: http:///
lt4256-3 7 42563fa pi fu ctio s uuu gate (pin 13): high side gate drive for the external n-channel mosfet. an internal charge pump guaranteesat least 10v of gate drive for v cc supply voltages above 20v and 4.5v of gate drive for v cc supply voltages between 10.8v and 20v. the rising slope of the voltage ongate is set by an external capacitor connected from gate to gnd and an internal 32 a pull-up current source from the charge pump output.if the current limit is reached, the gate voltage is adjusted to maintain a constant voltage across the sense resistor while the timing capacitor starts to charge. if the timer voltage ever exceeds 4.65v, gate is pulled low. gate is also pulled to gnd whenever uv is pulled low; the v cc supply voltage drops below the externally programmed undervoltage threshold, above the overvoltage thresholdor below the internal uvlo threshold (9.8v). gate is clamped internally to a maximum voltage of11.6v (typ) above v out under normal operating condi- tions. driving this pin beyond the clamp voltage maydamage the part. gate is also clamped to 2v (typ) below v out . when the gate is commanded off due to a fault condition, it is discharged quickly by a 62ma (typ) capable switch until gate is 2v (typ) below v out . when gate is below v out by 2v, the 62ma is reduced to 130 a to protect the lt4256-3 against damage if v out has large capacitance. a zener diode is needed between the gateand source of the external mosfet to protect its gate oxide under instantaneous short-circuit conditions. see applications information. sense (pin 15): current limit sense input. a sense resistor is placed in the supply path between v cc and sense. the current limit circuit regulates the voltageacross the sense resistor (v cc ?sense) to 55mv while in current limit when fb is 2v or higher. if fb drops below2v, the regulated voltage across the sense resistor de- creases linearly and stops at 14mv when fb is 0v. the open output also uses sense to detect when the output current is less than (3mv)/r5. to defeat current limit, connect sense to v cc . v cc (pin 16): input supply voltage. the positive supply input ranges from 10.8v to 80v for normal operation. i cc is typically 1.8ma. an internal circuit disables the lt4256-3for inputs less than 9.8v (typ). downloaded from: http:///
lt4256-3 8 42563fa block diagra w + + + 108 a v p v p 3mv logic 2v 14mv to 55mv 9.8v 4v4v v cc internal uv timer low timer high gnd 0.65v 4.65v + + 3.99v 3.99v 7v 100k pwrgd timer 4256 bd v cc sense v p gen fb ov 3 a uv retry gate v out open + + + charge pump and gate driver + ref gen 16 15 open circuit 4 12 13 5 9 8 current limit foldback 10 7 1 2 uvov downloaded from: http:///
lt4256-3 9 42563fa test circuit ti i g diagra s w u w figure 2. uv to gate timing figure 3. v out to pwrgd timing figure 4. sense to gate timing figure 1 v cc sense gate v out timer retry pwrgdopen fb ov uv 48v gnd 3v 3v 4256 f01 100pf + + + 48v + uv 4256 f02 gate v out +2v t plhuv 4v v out +2v t phluv 3.6v v cc ?sense 4256 f04 gate v cc t phlsense 55mv fb 4256 f03 pwrgd 1v t plhfb 4.45v 1v t phlfb 3.99v downloaded from: http:///
lt4256-3 10 42563fa applicatio s i for atio wu u u hot circuit insertionwhen circuit boards are inserted into a live backplane, the supply bypass capacitors on the boards draw high peak currents from the backplane power bus as they charge. the transient currents can permanently damage the con- nector pins and glitch the system supply, causing other boards in the system to reset. the lt4256-3 is designed to turn on a board? supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. the device also provides undervoltage and overvoltage as well as overcurrent protection while a power good output signal indicates when the output supply voltage is ready with a high output. power-up sequence an external n-channel mosfet pass transistor (q1) is placed in the power path to control the power up of the supply voltage (figure 5). resistor r5 provides current detection and capacitor c1 controls the gate slew rate. resistor r7 compensates the current control loop while r6 prevents high frequency oscillations in q1. when the power pins first make contact, transistor q1 isheld off. if the voltage on v cc is between the externally programmed undervoltage and overvoltage thresholds,v cc is above 9.8v and the voltage on timer is less than 4.65v (typ), transistor q1 will be turned on (figure 6). thevoltage on gate rises with a slope equal to 32 a/c1 and the supply inrush current is set at: i inrush = c l ?32 a/c1 (1) where c l is the total load capacitance. figure 5. 1.6a, 48v latchoff application figure 6. start-up waveforms 4256 f05 r5 0.025 ? lt4256-3 sense 1312 10 5 7 8 16 15 12 4 9 v cc gate v out fb pwrgd retry uvov timer gnd v in 48v gnd (short pin) q1 irf530 d1cmpz5241bs 11v r34.02k r24.02k r164.9k r7100 ? r94.02k r610 ? r836.5k pwrgd v out 48v1.6a r451k c l c233nf c3 0.01 f c110nf open uv = 36vov = 73v pwrgd = 40v d2smat70a + i out 500ma/div v out 50v/div 5ms/div 4256 f06 pwrgd 50v/div gate 50v/div c l = 125 f downloaded from: http:///
lt4256-3 11 42563fa applicatio s i for atio wu u u to reduce inrush current, increase c1 or decrease loadcapacitance. if the voltage across the current sense resis- tor r5 reaches v sensetrip , the inrush current will be lim- ited by the internal current limit circuitry. the voltage ongate is adjusted to maintain a constant voltage across the sense resistor and timer begins to charge. when the fb voltage goes above the low-to-high v fb threshold, pwrgd goes high.undervoltage and overvoltage detection the lt4256-3 uses uv and ov to monitor the v cc voltage to determine when it is safe to turn on the load and allowthe user the greatest flexibility for setting the operational thresholds. uv and ov are internally connected to an analog window comparator. any time that uv goes below 3.6v or ov goes above 4v, gate will be pulled low until the uv/ov voltages return to the normal operation voltage window (4v and 3.6v, respectively). the uv threshold should never be set below the internal uvlo threshold (9.8v typically) because the benefit of the uv? hysteresis will be lost, making the lt4256-3 more susceptible to noise (v cc must be at least 9.8v when uv is at its 3.6v threshold). uv is filtered with c3 to prevent noise spikes and capacitively coupled glitches from shut-ting down the lt4256-3 output erroneously. to calculate uv and ov thresholds, use the following equations: 4256 f07 r5 0.010 ? lt4256-3 sense 1310 5 7 8 16 d2smat70a 15 12 4 9 v cc gate fb 12 v out pwrgd retry uvov timer gnd v cc 48v (short pin) q1 irf540 d1cmpz5241bs 11v r34.02k r24.02k q2vn2222 r164.9k r7100 ? r94.02k r610 ? r836.5k v out 48v4a r451k c l c233nf c3 0.01 f off signal from mpu c110nf open uv = 36vov = 73v pwrgd = 40v gnd + figure 7. how to use a logic signal to control the lt4256-3 turn on/off rrr v v a r rr v b krrr k vv r rr vv rr r thuvlh thovlh thuvhlthovhl 123 4 12 3 12 4 1 2 20 1 2 3 200 3 36 1 1 23 4 36 1 12 3 =+ () ? ? ? ? ? ? () = + () ? ++ ? () =+ + ? ? ? ? ? ? () =+ + ? ? ? ? ? ? .;. where v thulh and v thovlh are the desired uv and ov threshold voltages when v cc is rising (l ?h). figure 7 shows how the lt4256-3 is commanded to shutoff with a logic signal. this is accomplished by pulling the gate of the open-drain mosfet, q2, (tied to uv) high. downloaded from: http:///
lt4256-3 12 42563fa applicatio s i for atio wu u u short-circuit protectionthe lt4256-3 features a programmable foldback current limit with an electronic circuit breaker that protects against short circuits or excessive load currents. the current limit is set by placing a sense resistor (r5) between v cc and sense. the current limit threshold is calculated as: i limit = 55mv/r5 (5) to limit excessive power dissipation in the pass transistorand to reduce voltage spikes on the input supply during short-circuit conditions at the output, the current folds back as a function of the output voltage, which is sensed internally on fb. if the lt4256-3 goes into current limit when the voltage on fb is 0v, the current limit circuit drives gate to force a constant 14mv drop across the sense resistor. as the output at fb increases, the voltage across the sense resistor increases until fb reaches 2v, at which point the voltage across the sense resistor is held constant at 55mv(see figure 8). for a 0.025 ? sense resistor, the typical current limit is set at 2200ma and folds back to 560ma when the output isshorted to ground. thus, mosfet peak power dissipation under short-circuit conditions is reduced from 106w to 27w. see the layout considerations section for important information about board layout to minimize current limit threshold error. the lt4256-3 also features a variable overcurrent re- sponse time. the time required for the part to regulate the gate voltage is a function of the voltage across the sense resistor connected between v cc and sense. this helps to eliminate sensitivity to current spikes and transients thatmight otherwise unnecessarily trigger a current limit re- sponse and increase mosfet dissipation. figure 9 shows the response time as a function of the overdrive at sense. figure 8. current limit sense voltage vs feedback pin voltage figure 9. response time to overcurrent 14mv 0v 2v fb 4256 f08 55mv v cc ?v sense 50 100 150 200 4256 f09 1210 86 4 2 response time ( s) v cc ?v sense (mv) 0 downloaded from: http:///
lt4256-3 13 42563fa applicatio s i for atio wu u u timertimer provides a method for programming the maximum time the part is allowed to operate in current limit. when the current limit circuitry is not active, timer is pulled to gnd by a 3 a current source. when the current limit circuitry becomes active, a 108 a pull-up current source is connected to timer and the voltage will rise with a slopeequal to 105 a/c timer as long as the circuitry stays active. once the desired maximum current limit time is known,the capacitor value is: cnf 25tms; c= 105 a 4.65v [] = [] ? (6) whenever timer reaches 4.65v (typ), the internal faultlatch is set causing gate to be pulled low and timer to be discharged to gnd by the 3 a current source. the part is not allowed to turn on again until the voltage on timerfalls below 0.65v (typ). whenever gate is commanded off by any fault condition, it is discharged with a high current, turning off the external mosfet. the waveform in figure 10 shows how the output latches off following a current fault. the drop across the sense resistor is held at 55mv as the timerramps up. once timer reaches its shutdown threshold (4.65v typically), the circuit latches off. automatic restart if retry is floating, then the device automatically restarts after a current overload fault. when the voltage at timer ramps back down to 0.65v(typ), the lt4256-3 turns on again. if the short-circuit condition at the output still exists, the cycle will repeat itself indefinitely. the duty cycle under short-circuit con- ditions is 3% which prevents q1 from overheating. fig- ure 11 shows representative waveforms during a short circuit. latch off operation if retry is grounded, the lt4256-3 will latch off after a current fault. after the part latches off, it may be com- manded to start back up. this is accomplished by cycling uv to ground and then back high (this command can only be accepted after timer discharges below the 0.65v typ threshold, which prevents overheating transistor q1). figure 10. latch off waveforms figure 11. retry waveforms 10ms/div 4256 f10 i out 500ma/div v out 50v/div timer 5v/div gate 50v/div i out 500ma/div v out 50v/div timer 5v/div gate 50v/div 10ms/div 4256 f11 downloaded from: http:///
lt4256-3 14 42563fa applicatio s i for atio wu u u therefore, using retry only, the lt4256-3 will eitherlatch off after an overcurrent fault condition or it will go into a hiccup mode. power good detection the lt4256-3 includes a comparator for monitoring the output voltage. the output voltage is sensed through the fb pin via an external resistor string. the comparator? output (pwrgd) is an open collector capable of operating from a pull-up as high as 80v. pwrgd can be used to directly enable/disable a power module with an active high enable input. figure 12 shows how to use pwrgd to control an active low enable input power module. signal inversion is accomplished by tran- sistor q2 and r10. the thresholds for the fb pin are 4.45v (low to high) and 3.99v (high to low). to calculate the pwrgd thresholds, use the following equations: r v krr k v 8= v r9, high to low (7) (8a) = 4.45v 1+ r8r9 , low to high (8b) thpwrgd thpwrgd 399 1 20 8 9 200 . ? ? ? ? ? ? ? + ? ? ? ? ? ? ? open pin/open fet detectionopen is an output which signals abnormally low load currents. when the voltage across the sense resistor is less than 3mv, the open collector pull-down device is shut off allowing open to be externally pulled high. open is always active when v cc is above 9.8v. if v cc is below 9.8v (the internal uvlo threshold), open is pulled low.open-circuit mosfets are detected with the lt4256-3 by monitoring the voltage across r5 with open while moni- toring the output voltage with pwrgd. an open fet condition is signalled when open is high and pwrgd is low (after the part has completed its start-up cycle). figure 12. active low enable pwrgd application 4256 f12 r5 100m ? lt4256-3 sense 1310 5 7 8 16 15 12 4 9 v cc gate fb 12 v out pwrgd retry uvov timer gnd v cc 24v (short pin) q1 irfz34vs d1cmpz5241bs 11v r34.02k r24.02k r132.4k r7100 ? r610 ? v out 24v400ma v logic r4 27k r8 14k c l r1051k c233nf c3 0.01 f c110nf open uv = 20vov = 40v pwrgd = 18v r94.02k q2zn3904 pwrgd gnd d2smat70a + downloaded from: http:///
lt4256-3 15 42563fa this open fet condition can be falsely signalled duringstart-up if the load is not activated until after pwrgd goes high. to avoid this false indication, open and pwrgd should not be polled for a period of time, t startup , given by: t vc a startup cc = 31 32 (9) this can be accomplished either by a microcontroller (ifavailable) or by placing an rc filter as shown in figure 13. once the open voltage exceeds the monitoring logic thresh- old, v thresh , and pwrgd is low, an open fet condition is signalled. in order to prevent a false indication, the rcproduct should be set with the following equation: rc vc a v vv cc logic logic thresh > ? ? ? ? ? ? ? ? ? ? ? ? 31 32 ln (10) another condition that can cause a false indication is if thelt4256-3 goes into current limit during start-up. this will cause t startup to be longer than calculated. also, if the lt4256-3 stays in current limit long enough for timer tofully charge up to its threshold, the lt4256-3 will either latch off (retry = 0) or go into the current limit hiccup mode (retry = floating). in either case, an open fet condition will be falsely signalled. if the lt4256-3 does go into current limit during start-up, c1 can be increased (see power-up sequence). applicatio s i for atio wu u u supply transient protectionthe lt4256-3 is 100% tested and guaranteed to be safe from damage with supply voltages up to 80v. however, voltage transients above 100v may cause permanent damage. during a short-circuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage transients which could exceed 100v. to minimize the voltage transients, the power trace parasitic inductance should be minimized by using wider traces or heavier trace plating and a bypass capacitor should be placed between v cc and gnd. a surge suppres- sor (transzorb ) at the input can also prevent damage from voltage transients.gate pin a curve of gate drive vs v cc is shown in figure 14. gate is clamped to a maximum voltage of 12.8v above v out . this clamp is designed to withstand the internal chargepump current. an external zener diode must be used as shown in all applications. at a minimum input supply voltage of 10.8v, the minimum gate drive voltage is 4.5v. when the input supply voltage is higher than 20v, the gate drive voltage is at least 10v and a standard threshold mosfet can be used. in applications from 12v to 15v range, a logic level mosfet must be used. figure 13. delay circuit for open fet detection 4 r c 4256 f13 open lt4256-3 tomonitoring logic v logic internal open collector pull-down figure 14. ? v gate vs v cc v cc (v) 10 3 ? v gate (v) 4 6 7 8 1310 30 50 60 4256 f14 5 11 12 9 20 40 70 80 transzorb is a registered trademark of general instruments, gsi. downloaded from: http:///
lt4256-3 16 42563fa in some applications it may be possible for v out to ring below ground (due to the parasitic trace inductance).higher current applications, especially where the output load is physically far away from the lt4256-3 will be more susceptible to these transients. this is normal and the lt4256-3 has been designed to allow for some ringing below ground. however, if the application is such that v out can ring more than 3v below ground, damage may occur to the lt4256-3 and an external diode, d2, fromground (anode) to v out (cathode) will have to be added to the circuit as shown in figure 15 (it is critical that thereverse breakdown voltage of the diode be higher than the highest expected v cc voltage). a capacitor placed from ground to v out directly at the lt4256-3 pins can help reduce the amount of ringing on v out but it may not be enough for some applications.during a fault condition, the lt4256-3 pulls down on gate with a switch capable of sinking about 62ma. once gate drops below the output voltage by a diode forward voltage, the external zener will forward bias and v out will also be discharged to gnd. in addition to the gatecapacitance, the output capacitance will be discharged through the lt4256-3. in applications utilizing very large external n-channel mosfets, the possibility exists for the mosfet to turn on when initially inserted into a live backplane (before the applicatio s i for atio wu u u lt4256-3 becomes active and pulls down on gate). thisis due to the mosfet intrinsic drain to gate capacitance forcing current into r7 and c1 when the drain voltage steps up from ground to v cc with an extremely fast rise time. to alleviate this situation, a diode, d3, should be putacross r7 with the cathode connected to c1 as shown in figure 16. whenever the lt4256-3 turns the mosfet off, gate pulls the mosfet gate to ground with an open collector capable of sinking 62ma. if the output is held up by a large reservoir capacitor, the stored energy is dissipated in the pull-down transistor via a sneak path through the (now forward biased) zener, d1. the lt4256-3 has a propri- etary feature that reduces on-chip power dissipation by sensing when the mosfet is off and reducing the pull- down current significantly. see v gate turn-off for more information about using this feature.v gate turn-off the lt4256-3 has a proprietary feature that reducespower dissipation by sensing when the mosfet is off and reducing the pull-down current significantly. as the gate pin is discharged during any fault, the lt4256-3 monitors the gate pin and v out pin. when the gate pin is 2v below v out , the pull-down current is reduced from 62ma to about 130 a. figure 15. negative output voltage protection diode application 4256 f14 r5 0.010 ? lt4256-3 sense 1310 5 7 8 16 15 12 4 9 v cc gate fb 12 v out pwrgd retry uvov timer gnd v cc 48v (short pin) q1 irf540 d1cmpz5241bs 11v d3mra4003t3 r34.02k r24.02k r164.9k r7100 ? r94.02k r610 ? r836.5k v out 48v4a r451k c l c233nf c3 0.01 f c110nf open uv = 36vov = 73v pwrgd = 40v gnd d2smat70a + downloaded from: http:///
lt4256-3 17 42563fa applicatio s i for atio wu u u figure 16. high dv/dt mosfet turn-on protection circuit 4256 f16 r5 0.033 ? lt4256-3 sense 1310 125 7 8 16 15 12 4 9 v cc gate v out fb pwrgd retry uvov timer gnd v cc 48v (short pin) q1 irf530 d1cmpz5241bs 11v d31n4148w r34.02k r24.02k r164.9k r7100 ? r94.02k r610 ? r836.5k v out 48v1.2a r427k c l c233nf c3 0.1 f c110nf open uv = 36vov = 73v pwrgd = 40v gnd d2smat70a + figure 17. enhanced output pull-down circuit in order to use this feature as designed, a bidirectionalzener diode is needed for d1. when the lt4256-3 com- mands the mosfet off (and a bidirectional zener is used), the output discharges very slowly (t off = (c load ?v out )/ 130 a). several variations can be implemented to dis- charge the output faster. the recommeded method isshown in figure 17 and uses an external pnp transistor, diode and resistor to discharge the output quickly. 4256 f17 r5 0.010 ? lt4256-3 sense 13 r prog q22n4920 d3 1n4148 r b 18k 105 7 8 16 15 12 4 9 v cc gate fb 12 v out pwrgd retry uvov timer gnd v cc 48v (short pin) q1 irf540 d1cmpz5241bs 11v r34.02k r24.02k r164.9k r7100 ? r94.02k r61k r836.5k v out 48v4a r451k c l c233nf c3 0.01 f c110nf open uv = 36vov = 73v pwrgd = 40v gnd d2smat70a + the equation to set the nominal discharge current is: i r a dischg prog = () 5000 130 (11) where r prog must be less than 1k. the maximum current equation is: i r a max prog = () 7000 350 (12) downloaded from: http:///
lt4256-3 18 42563fa applicatio s i for atio wu u u figure 18. recommended component placement layout considerationsto achieve accurate current sensing, a kelvin connection to the current sense resistor (r5 in typical application circuit) is recommended. note that 1oz copper exhibits a sheet resistance of about 530 ? / ? . small resistances can cause large errors in high current applications. noise immunity will be improved significantly by locating resis-tor dividers close to the pins with short v cc and gnd traces. the minimum trace width for 1oz copper foil is0.02" per amp to make sure the trace stays at a reasonable temperature. 0.03" per amp or wider is recommended. figure 18 shows a layout that meets these requirements. c1 42563 f18 v out v in gnd r8 r7 r5 q1 d1 r6 r9 r3 r1 d2 r2 lt4256-3 downloaded from: http:///
lt4256-3 19 42563fa u package descriptio gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note:1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale downloaded from: http:///
lt4256-3 20 42563fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts part number description comments lt1641-1/lt1641-2 positive 48v hot swap controller in so-8 9v to 80v operation, active current limit, autoretry/latchoff ltc4211 single hot swap controller with multifunction current control 2.5v to 16.5v, active inrush limiting, dual level cicuit br eaker ltc4251 48v hot swap controller in sot-23 floating supply from 15v, active current limiting, fast circuit breaker ltc4252-1/ltc4252-2 48v hot swap controller in msop floating supply from ?5v, active current limiting, power good output ltc4253 48v hot swap controller and supply sequencer floating supply from ?5v, active current limiting, enables three dc/dc converters lt4254 positive high voltage hot swap controller 10.8v to 36v operation, open-circuit detection lt4256-1/lt4256-2 positive high voltage hot swap controller 10.8v to 80v operation, active current limit, autoretry/latchoff ? linear technology corporation 2004 lt/lwi/lt 0705 rev a printed in usa applicatio s i for atio wu u u r5 0.020 ? lt4256-3 sense v cc gate fb v out pwrgd retry uvov timer gnd d3cmpz5241bs 11v r34.02k r24.02k r164.9k r7 100 ? r9 4.02k r6 10 ? r836.5k pwrgd2 v out2 48v2a r451k c l2 33nf c3 0.01 f c1 10nf open uv = 36vov = 73v pwrgd = 40v + 4256 ta03 r5 0.020 ? lt4256-3 sense v cc gate fb v out pwrgd retry uvov timer gnd v in 48v gnd (short pin) q1 irf540 q2 irf540 d1cmpz5241bs 11v r34.02k r24.02k r164.9k r7 100 ? r9 4.02k r6 10 ? r836.5k pwrgd1 v out1 48v2a r451k c l1 c233nf c3 0.01 f c1 10nf open d2smat70a uv = 36vov = 73v pwrgd = 40v + dual 48v supply sequencing application v in 50v/div v out1 50v/div v out2 50v/div 5ms/div 4256 ta04 pwrgd1 50v/div c l1 = 200 f c l2 = 147 f downloaded from: http:///

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